Liquid crystal display device and touch panel

ABSTRACT

A semiconductor layer of a transistor is formed of an oxide semiconductor film including a crystal part. An organic resin film covering the transistor is formed. By treatment such as drying treatment on the organic resin film in a cell process, variations in the threshold voltage of the oxide semiconductor transistor due to moisture can be suppressed. A common electrode faces a pixel electrode. The common electrode and the pixel electrode are formed over the organic resin film with an insulating film provided therebetween. Therefore, a capacitor can be provided to a liquid crystal element if a pixel does not include a wiring for a storage capacitor. An antistatic electrode is provided on the outer side of a color filter substrate and the capacitance between the antistatic electrode and the common electrode is utilized, so that the liquid crystal display device can be used as a touch panel.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a liquid crystal display device including a transistor using an oxide semiconductor and a touch panel including the liquid crystal display device.

2. Description of the Related Art

Transistors which are used for many liquid crystal display devices and organic EL display devices have been formed using a silicon semiconductor film such as an amorphous silicon film or a polycrystalline silicon film.

Instead of the silicon semiconductor film, a technique in which an oxide semiconductor film is used for transistors has attracted attention.

For example, a technique is disclosed in which a transistor manufactured using an In—Ga—Zn oxide film as an oxide semiconductor is used as a switching element or the like of a pixel (see Patent Documents 1 and 2).

Further, we develop a technique in which an oxide semiconductor film having a noble crystal structure is manufactured over a glass substrate (see Non-Patent Document 1).

REFERENCE Patent Document

-   [Patent Document 1] Japanese Published Patent Application No.     2006-165528 -   [Patent Document 2] Japanese Published Patent Application No.     2007-096055

Non-Patent Document

-   [Non-Patent Document 1] Shunpei Yamazaki, et al., “Research,     Development, and Application of Crystalline Oxide Semiconductor”,     SID 2012 DIGEST, pp. 183-186

An oxide semiconductor is a semiconductor material whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon. Thus, a transistor including an oxide semiconductor film (hereinafter referred to as an oxide semiconductor transistor) can have extremely lower off-state current than a transistor including an amorphous silicon film or a polycrystalline silicon film. As a result, when a backplane (circuit board) of a liquid crystal display device or an organic EL display device is manufactured using an oxide semiconductor transistor, the display device can have low power consumption.

In addition, with a transistor including a crystalline oxide semiconductor film, the density of pixels can be increased, and high definition of a display device can be achieved (see Non-patent Document 1).

In view of fossil fuel exhaustion, environmental problems, and the like, all kinds of electronic devices are required to consume less power. Liquid crystal display devices are no exception. It is known that power consumption of liquid crystal display devices varies depending on a method for applying an electric field to a liquid crystal layer (display mode). Power consumption for changing alignment of a liquid crystal material (rewriting data of a pixel) in a horizontal electric field mode is lower than that in a vertical electric field mode such as a twisted nematic (TN) mode or a vertical alignment (VA) mode.

Since a liquid crystal display device of a horizontal electric field mode can have a wider viewing angle than that of a vertical electric field mode, in recent years, liquid crystal display devices with a variety of screen sizes are used as display devices of television devices, mobile devices, and the like.

In a liquid crystal display device of a horizontal electric field mode, a pixel electrode and a common electrode are provided on a substrate where a transistor is manufactured, and an electric field in a substantially horizontal direction is applied to a liquid crystal molecule. Typical examples of a horizontal electric field mode are an in-plane-switching (IPS) mode and a fringe field switching (FFS) mode. Note that an FFS mode is classified into an oblique electric field mode in some cases.

By a combination of a horizontal electric field mode and a transistor including a crystalline oxide semiconductor film, high definition and low power consumption of a liquid crystal display device can be achieved, and high performance of a touch panel can also be achieved.

On the other hand, improvement in reliability is a big issue for mass production of a liquid crystal display device whose backplane is formed using an oxide semiconductor.

In view of the above, an object of one embodiment of the present invention is to provide a highly reliable liquid crystal display device whose backplane is formed using an oxide semiconductor.

SUMMARY OF THE INVENTION

It is found from our research that entry of water into an oxide semiconductor film is one of big facts of a change in electric characteristics of an oxide semiconductor transistor. Entry of water into the oxide semiconductor film increases carrier density, so that electric characteristics of the transistor are varied.

For that reason, a liquid crystal display device is manufactured using a material containing water as little as possible and by a structure and a manufacturing method which prevents entry of water as much as possible, which leads to resolution of decrease in reliability.

However, limitation of a material causes new problems in that display quality of a liquid crystal display device is decreased and that existing equipment in a manufacturing factory of liquid crystal display devices cannot be used; thus, early practical application of liquid crystal display devices including an oxide semiconductor is hindered.

For example, in order to suppress defective orientation of a liquid crystal molecule, it is preferable that a planarization film be formed as a base film of a pixel electrode. Since the planarization film needs to be formed thick so as to reduce unevenness of a transistor, an organic resin film is generally used as a planarization film. However, an organic resin film has a higher hygroscopic property than an inorganic insulating film; thus, there is a problem in combination with an oxide semiconductor transistor.

One embodiment of the present invention is a liquid crystal display device in which a liquid crystal layer is sealed between a pair of substrates, a pixel electrode and a common electrode are formed over an organic resin film, an alignment film is formed, and then, drying treatment is performed between the pair of substrates before the liquid crystal layer is sealed. Steps from the drying treatment to sealing of the liquid crystal layer are performed without exposure to the air.

Further, one embodiment of the present invention is a touch panel including the liquid crystal display device of the above embodiment.

According to the technique disclosed in this specification, a liquid crystal display device having as high reliability as a practical level, whose backplane is formed using an oxide semiconductor, can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIG. 1 is a plan view illustrating a structural example of a liquid crystal panel;

FIG. 2 is a cross-sectional view illustrating a structural example of the liquid crystal panel, taken along line B1-B2 in FIG. 1;

FIG. 3 is a plan view illustrating a structural example of a pixel;

FIG. 4 is a cross-sectional view of the pixel taken along line A1-A2 in FIG. 3;

FIG. 5 is a cross-sectional view of the pixel taken along line A3-A4 in FIG. 3;

FIG. 6 is a cross-sectional view illustrating an example of a connection structure of a common electrode and a terminal portion;

FIG. 7 is a cross-sectional view illustrating an example of a connection structure of wirings (electrodes) of a liquid crystal panel;

FIGS. 8A to 8D are cross-sectional views illustrating an example of a method for manufacturing a transistor;

FIGS. 9A to 9C are cross-sectional views illustrating an example of steps following the step in FIG. 8D;

FIG. 10A is a block diagram illustrating a structural example of a liquid crystal panel, and FIG. 10B is a circuit diagram illustrating a structural example of a pixel;

FIG. 11 is a table showing an example of specifications of a liquid crystal panel;

FIG. 12 is a cross-sectional view illustrating a structure example of a touch panel including the liquid crystal panel in FIG. 1;

FIG. 13 is a plan view illustrating a structure example of a touch sensor of the touch panel in FIG. 12;

FIG. 14A is a cross-sectional view of the touch panel taken along line C1-C2 in FIG. 13 and FIG. 14B is a plan view of a region 240 in FIG. 13;

FIG. 15A is a perspective exploded view illustrating a structural example of a touch sensor, and FIG. 15B is a plan view illustrating a structural example of an electrode of the touch sensor;

FIG. 16 is a cross-sectional view of a structural example of a touch sensor;

FIG. 17 is an equivalent circuit diagram of an intersection of two electrodes of a touch sensor;

FIG. 18 is a diagram for a mask illustrating a structural example of a touch sensor;

FIG. 19 is a block diagram illustrating a structural example of a liquid crystal display device including the liquid crystal panel in FIG. 1;

FIG. 20 is a timing chart illustrating an example of a method for driving the liquid crystal display device in FIG. 19;

FIGS. 21A to 21F are perspective views each illustrating a structural example of an electronic device including a liquid crystal panel or a touch panel;

FIG. 22 is a graph showing the intensities of gas molecules having a mass-to-charge ratio (m/z) of 18 and being released from circuit boards (each including an organic resin film) of a liquid crystal panel, which are obtained by TDS;

FIG. 23 is a graph showing the intensities of gas molecules having a mass-to-charge ratio (m/z) of 18 and being released from circuit boards (not including an organic resin film) of a liquid crystal panel, which are obtained by TDS;

FIG. 24 is a graph showing a change in an operation margin width (voltage) with respect to an operation time of a scan line driver circuit (subjected to drying treatment);

FIG. 25 is a graph showing a change in an operation margin width (voltage) with respect to an operation time of a scan line driver circuit (not subjected to drying treatment);

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following description and it is easily understood by those skilled in the art that the mode and details can be variously changed without departing from the scope and spirit of the present invention. Accordingly, the invention should not be construed as being limited to the description of the embodiments below.

Note that in the drawings used for the description of the embodiments of the invention, the same portions or portions having similar functions are denoted by the same reference numerals, and repeated description thereof is omitted.

Embodiment 1 <Structure of Liquid Crystal Panel>

A liquid crystal panel of one embodiment of the present invention is described with reference to FIG. 1 to FIG. 6 and FIGS. 10A and 10B.

FIG. 10A is a block diagram illustrating a structural example of a liquid crystal panel 10. The liquid crystal panel 10 includes a display portion 30, a scan line driver circuit 41, a scan line driver circuit 42, and a data line driver circuit 43. In the liquid crystal panel 10, the driver circuits 41 to 43 and the display portion 30 are formed over the same substrate, a board 100; thus, the liquid crystal panel 10 is also referred to as a liquid crystal module. The liquid crystal panel 10, a control circuit thereof, a power supply circuit, a back light module, and the like are incorporated in a housing, so that a liquid crystal display device is completed.

The display portion 30 includes a plurality of pixels 31 each of which is connected to a scan line 110 and a data line 111. FIG. 10B is a circuit diagram showing a structural example of the pixel 31.

The pixel 31 includes a transistor 35 and a liquid crystal element 36. The transistor 35 is a switching element which controls electrical connection between the liquid crystal element 36 and the data line 111. The transistor 35 is turned on or off by a scan signal input from its gate via the scan line 110.

FIG. 1 is a plan view showing an example of a structure of the liquid crystal panel 10. FIG. 2 is a cross-sectional view showing an example of the structure of the liquid crystal panel 10, along line B1-B2 in FIG. 1. The liquid crystal panel 10 includes the display portion 30, the scan line driver circuit 41, the scan line driver circuit 42, the data line driver circuit 43, and a terminal portion 60.

FIG. 3 is a plan view illustrating an example of a structure of the pixel 31. FIG. 4 is a cross-sectional view illustrating an example of the structure of the pixel, along line A1-A2 in FIG. 3. FIG. 5 is a cross-sectional view illustrating an example of the structure of the pixel taken along line A3-A4 in FIG. 3. Here, the pixel 31 of an FFS mode is used for the liquid crystal panel 10.

A transistor using an oxide semiconductor is formed in each of the display portion 30, the scan line driver circuits 41 and 42, and the data line driver circuit 43. A transistor 45 of the data line driver circuit 43 is shown in FIG. 2, and a transistor 35 of the pixel 31 is shown in FIG. 4. The transistors of the display portion 30 and the driver circuits 41 to 43 have the same structure. The transistors of the display portion 30 and the driver circuits 41 to 43 are bottom-gate transistors in which semiconductor layers are formed using oxide semiconductors including crystal parts.

The scan lines 110 in the odd-numbered rows are connected to one of the scan line driver circuits 41 and 42 and the scan lines 110 in even-numbered rows are connected to the other thereof. The data lines 111 are connected to the data line driver circuit 43. The transistor 35 of the pixel 31 is connected to the scan line 110 and the data line 111.

There is a liquid crystal layer 140 sealed with a sealing member 215 between the substrate 100 and a substrate 200. The cell gap of the liquid crystal panel 10 is maintained by a spacer 241 formed over the substrate 200 (see FIG. 5). As shown in FIG. 3 and FIG. 5, the spacer 241 is formed in a region where the scan line 110 and the data line 111 overlaps with each other. Such a region does not contribute to display because it is a region where the alignment of the liquid crystal material is disordered. When the spacer 241 is formed in such a region, the aperture ratio of the pixel 31 can be increased to 50% or more.

Over the substrate 100, a terminal portion 60 connected to an FPC 61 is formed outside the sealing member 215. In an upper layer of the terminal portion 60, an electrode 162 is formed using the same transparent conductive film as a common electrode 115, and the FPC 61 and the electrode 162 are electrically connected to each other through an anisotropic conductive film 65. The wiring 161 is electrically connected to the display portion 30, the driver circuit 41, the driver circuit 42, and the driver circuit 43 and is formed using a conductive film forming the data line 111. Note that a wiring connecting the electrode 162 to the display portion 30 and the driver circuits 41 to 43 can be formed using the same conductive film as the scan line 110.

<Pixel>

In the pixel 31, over an organic resin film 135, the common electrode 115 and a pixel electrode 116 face each other with an insulating film 136 provided therebetween. The common electrode 115 is formed as one electrode in the display portion 30, and in each of the pixels 31, an opening is formed in a connection portion between the pixel electrode 116 and the transistor 35.

The pixel electrode 116 is divided for each of the pixels 31, and the pixel electrode 116 included in each of the pixels 31 has a striped region. The liquid crystal element 36 (see FIG. 10B) in the pixel 31 includes the common electrode 115, the pixel electrode 116, and the liquid crystal layer 140. Alignment of the liquid crystal material of the liquid crystal layer 140 is changed by the action of an electric field generated between the common electrode 115 and the pixel electrode 116.

Note that in the common electrode 115, a slit-shaped opening can be formed in a portion overlapping with the pixel electrode 116.

Further, a capacitor C1 is formed in a region where the pixel electrode 116 and the common electrode 115 overlap with each other with the insulating film 136 provided therebetween (see FIG. 10B). Thus, a capacitor C2 formed by additionally forming an auxiliary capacitor wiring in the pixel 31 is not necessary. In other words, as a storage capacitor of the liquid crystal element 36, the capacitor C1 (>0 fF) including the pixel electrode 116, the common electrode 115, and the insulating film 136 is provided and the capacitor C2 using the auxiliary capacitor wiring as an electrode is not provided. That is, the capacitance value of the capacitor C1 exceeds 0 (fF) and can be approximately several hundred (fF); on the other hand, that of the capacitor C2 is 0 (fF).

Thus, since an auxiliary capacitor wiring which decreases an aperture ratio is not formed in the pixel 31 and the capacitor C1 is provided in parallel to the liquid crystal element 36, the aperture ratio can be increased. The aperture ratio can be increased to 50% or greater, further 60% or greater.

Over the substrate 200, a black matrix 210, a color filter 211, an overcoat 212, and an alignment film 213 are formed. The color filter 211 is formed in a region overlapping with the pixel electrode 116. The black matrix 210 is formed using an organic resin film and is provided to cover a region which does not contribute to display and in which the scan line 110, the data line 111, and the like are formed.

As illustrated in FIG. 6, the common electrode 115 is electrically connected to a wiring 117 over an insulating film 131. The wiring 117 is formed outside the display portion 30 and is electrically connected to the electrode 162 in the terminal portion 60 in a manner similar to that of the wiring 161 in FIG. 2. With such a structure, a constant potential can be applied to the common electrode 115 from the outside of the liquid crystal panel 10.

Although the pixel 31 is an FFS mode pixel as shown in FIG. 3, a transversal electric field mode pixel such as an IPS mode pixel may be used. Alternatively, a vertical electric field mode pixel in which a common electrode is provided on the substrate 200 side may be used. Electric field is less disordered when the screen is touched by a finger or the like in a transversal electric field mode than in a vertical electric field mode; thus, the transversal electric field mode is suitable for a liquid crystal touch panel.

An FFS mode liquid crystal panel can have a wider viewing angle and higher contrast than an IPS mode liquid crystal panel and can be driven at lower voltage than an IPS mode one; thus, it is extremely preferable that by using a transistor including an oxide semiconductor, a high definition display device of a mobile electronic device can be obtained.

<Method for Manufacturing Transistor>

A method for manufacturing a circuit board of the liquid crystal panel 10 illustrated in FIG. 1 is described below.

First, a method for manufacturing transistors in the display portion 30 and the driver circuits 41 to 43 are described with reference to FIGS. 8A to 8D and FIGS. 9A to 9C. FIGS. 8A to 8D and FIGS. 9A to 9C are cross-sectional views illustrating an example of a method for manufacturing the transistor 35 in the display portion 30, and the transistors in the driver circuits 41 to 43 which have the same structure are formed over the substrate 100 at the same time as the transistor 35.

As illustrated in FIG. 8A, a conductive film 301 which forms a wiring and an electrode in the first layer is formed over the substrate 100.

As the substrate 100, for example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like is used. The same can be applied to the substrate 200.

A glass substrate is preferable as the substrate 100. In the case where a large-sized substrate having the size of the fifth generation (1000 mm×1200 mm or 1300 mm×1500 mm), the sixth generation (1500 mm×1800 mm), the seventh generation (1870 mm×2200 mm), the eighth generation (2200 mm×2500 mm), the ninth generation (2400 mm×2800 mm), the tenth generation (2880 mm×3130 mm), or the like is used, minute processing might become difficult owing to shrinkage of the substrate 100 caused by heat treatment or the like in the manufacturing process of a liquid crystal display device. Therefore, in the case where the above-described large glass substrate is used as the substrate 100, a substrate which is unlikely to shrink through the heat treatment is preferably used. For example, as the substrate 100, it is possible to use a large glass substrate in which the amount of shrinkage after heat treatment for one hour at 400° C., preferably 450° C., more preferably 500° C. is less than or equal to 10 ppm, preferably less than or equal to 5 ppm, more preferably less than or equal to 3 ppm.

As the conductive film 301, a single layer or two or more layers of a film including a conductive material containing one or more kinds of aluminum, titanium, chromium, cobalt, nickel, copper, yttrium, zirconium, molybdenum, ruthenium, silver, tantalum, and tungsten are preferably formed. For example, as the conductive film 301, a film in which a copper film is stacked over a tungsten nitride film or a single layer film of tungsten can be formed.

Next, a gate electrode of the transistor is formed by a photolithography process and an etching step. A mask formed of a resist (hereinafter referred to as a resist mask) is formed over the conductive film 301 by using a first photomask and then the conductive film 301 is etched, so that the scan line 110 is formed. Then, the resist mask is removed (FIG. 8B).

As illustrated in FIG. 7, a wiring 171 is formed together with the scan line 110. FIG. 7 is a cross-sectional view illustrating an example of a connection structure of wirings (electrodes) formed outside the display portion 30 and illustrates a structure in which a wiring/electrode in a first layer and a wiring/electrode in a second layer are connected to each other. Such a connection structure is applied to the driver circuits 41 to 43, a lead wiring, and the like.

The insulating film 131 is formed to cover the scan line 110 (wiring/electrode in the first layer), and a three-layer stack of oxide semiconductor films 311 to 313 is formed over the insulating film 131. Here, the oxide semiconductor films 311 to 313 are formed by a sputtering method using an In—Ga—Zn oxide film.

The insulating film 131 serves as a gate insulating film of the transistor. The insulating film 131 may be formed of a single layer or a stacked layer using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.

For example, in the case of using the insulating film 131 having a two-layer structure, a multilayer film including a silicon nitride film as the first layer and a silicon oxide film as the second layer may be used. The silicon oxide film in the second layer can be a silicon oxynitride film. The silicon nitride film in the first layer can be replaced with a silicon nitride oxide film.

As the silicon oxide film, a silicon oxide film with a low defect density is preferably used. Specifically, a silicon oxide film which has a spin density of 3×10¹⁷ spins/cm³ or less, preferably 5×10¹⁶ spins/cm³ or less is used. The spin density is obtained by a signal at a g-factor of 2.001 in electron spin resonance (ESR). As the silicon oxide film, a silicon oxide film having excess oxygen is preferably used. As the silicon nitride film, a silicon nitride film from which hydrogen and ammonia are less released is used. The amount of released hydrogen and ammonia is preferably measured by thermal desorption spectroscopy (TDS) analysis.

Note that silicon nitride oxide refers to an insulating material that contains more nitrogen than oxygen, whereas silicon oxynitride refers to an insulating material that contains more oxygen than nitrogen.

The three-layer stack of the oxide semiconductor films 311 to 313 forms the semiconductor layer 120 in the transistor. Although the three-layer stack of the oxide semiconductor films (311 to 313) is formed here (FIG. 8C), a single-layer structure or another stacked-layer structure may be employed.

Next, the semiconductor layer 120 of the transistor is formed by a photolithography process and an etching step. A resist mask is formed over the oxide semiconductor film 311 by using a second photomask and then the oxide semiconductor films 311 to 313 are etched, so that the semiconductor layer 120 is formed. Then, the resist mask is removed (FIG. 8D).

The semiconductor layer 120 of the transistor will be described in Embodiment 2. Here, the oxide semiconductor films 311 to 313 are provided such that a channel of the transistor is formed in mainly the oxide semiconductor film 312 of the semiconductor layer 120.

As shown in FIG. 9A, a conductive film 302 forming a wiring and an electrode in a second layer is formed over the entire surface of the substrate 100. The conductive film 302 can be formed in a manner similar to the conductive film 301. Here, the conductive film 302 has a three-layered structure. The first layer and the third layer are formed of a titanium film, and the second layer is formed of an aluminum film. The titanium film and the aluminum film are formed by a sputtering method.

Then, with the use of a third photomask, a resist mask is formed over the conductive film 302 and the insulating film 131. With the use of the resist mask, the conductive film 302 is etched to form the data line 111 connected to the semiconductor layer 120 and the electrode 112 (FIG. 9B). The data line 111 and the electrode 112 serve as a source electrode and a drain electrode of the transistor.

In addition, the wiring 161 illustrated in FIG. 2, the wiring 117 in FIG. 6, a wiring 172 in FIG. 7, and the like are formed using the conductive film 302 as the wiring/electrode in the second layer. The wiring 117 in FIG. 6 is a lead wiring for connecting the common electrode 115 to the terminal portion 60.

Then, an inorganic insulating film is formed to cover the entire surface of the substrate 100. Here, a stack of insulating films 132 to 134 formed using inorganic insulating materials is formed. It is particularly preferable that the insulating films 132 and 133 be oxide insulating films and the insulating film 133 be a nitride insulating film. Further, the use of a nitride insulating film as the insulating film 133 can suppress entry of impurities such as hydrogen and water into the semiconductor layer of the transistor from the outside. Note that the insulating film 132 is not necessarily provided.

Further, in the case where one or both of the insulating films 132 and 134 are oxide films, the oxide film in which the oxygen content is higher than that in the stoichiometric composition is preferably used. In that case, oxygen can be prevented from being released from the oxide semiconductor films 311 to 313, and the oxygen contained in an oxygen excess region can be transferred to the oxide semiconductor film to fill oxygen vacancies.

For example, when an oxide insulating film having the following feature is used, oxygen vacancies in the oxide semiconductor film can be filled. The feature of the oxide insulating film is that the number of oxygen molecules released from the oxide insulating film is greater than or equal to 1.0×10¹⁸ molecules/cm³ when measured by thermal desorption spectroscopy (hereinafter referred to as thermal desorption spectroscopy (TDS)). Note that an oxide insulating film partly including a region in which the oxygen content is higher than that in the stoichiometric composition (oxygen excess region) may be used as one of or both the insulating film 132 and the insulating film 133. When such an oxygen excess region is present in a region overlapping with at least the semiconductor layer 120 including the oxide semiconductor films 311 to 313, oxygen is prevented from being released from the oxide semiconductor films 311 to 313 and the oxygen contained in the oxygen excess region can enter the oxide semiconductor films 311 to 313 to fill oxygen vacancies.

In the case where the insulating film 133 is an oxide insulating film in which the oxygen content is higher than that in the stoichiometric composition, the insulating film 132 is preferably an oxide insulating film through which oxygen penetrates. Oxygen which enters the insulating film 132 from the outside partly remains in the insulating film 132. Further, oxygen which is contained in the insulating film 132 from the first is released from the insulating film 132 to the outside in some cases. Thus, the insulating film 132 is preferably an oxide insulating film having a high coefficient of diffusion of oxygen.

The thickness of the insulating film 132 can be greater than or equal to 5 nm and less than or equal to 150 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, further preferably greater than or equal to 10 nm and less than or equal to 30 nm. The insulating film 131 can have a thickness of greater than or equal to 30 nm and less than or equal to 500 nm, preferably greater than or equal to 150 nm and less than or equal to 400 nm.

In the case where a nitride insulating film is used as the insulating film 134, an insulating film having a barrier property against nitrogen is preferably used as one of or both the insulating film 132 and the insulating film 134. For example, a dense oxide insulating film can have a barrier property against nitrogen. Specifically, an oxide insulating film which can be etched at a rate of less than or equal to 10 nm per minute when the temperature is 25° C. and 0.5 wt % of fluoric acid is used is preferably used.

In the case where an oxide insulating film containing nitrogen, such as a silicon oxynitride film or a silicon nitride oxide film, is used as one or both of the insulating film 132 and the insulating film 134, the nitrogen concentration measured by SIMS is greater than or equal to the lower limit of measurement by secondary ion mass spectrometry (SIMS) and less than 3×10²⁰ atoms/cm³, preferably greater than or equal to 1×10¹⁸ atoms/cm³ and less than or equal to 1×10²⁰ atoms/cm³. In that case, the amount of nitrogen which enters the semiconductor layer 120 containing the oxide semiconductor included in the transistor 35 can be reduced and the number of defects in the nitrogen-containing oxide insulating film itself can be reduced.

The insulating film 132 can be formed under the following conditions. The substrate placed in a treatment chamber of the PE-CVD apparatus, which is vacuum-evacuated, is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., a deposition gas containing silicon and an oxidizing gas are introduced as a source gas into the treatment chamber, the pressure in the treatment chamber is greater than or equal to 20 Pa and less than or equal to 250 Pa, preferably greater than or equal to 40 Pa and less than or equal to 200 Pa, and high-frequency power is supplied to an electrode provided in the treatment chamber.

Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, or the like can be used.

As the insulating film 134, a nitride insulating film with a low hydrogen content may be provided. The nitride insulating film in which the number of hydrogen molecules released from the nitride insulating film is less than 5.0×10²¹ molecules/cm³, preferably less than 3.0×10²¹ molecules/cm³, more preferably less than 1.0×10²¹ molecules/cm³ when measured by TDS spectroscopy.

The insulating film 134 has a thickness large enough to prevent entry of impurities such as hydrogen and water into the transistor from the outside, for example greater than or equal to 50 nm and less than or equal to 200 nm, preferably greater than or equal to 50 nm and less than or equal to 150 nm, and further preferably greater than or equal to 50 nm and less than or equal to 100 nm.

The insulating films 132 to 134 can be formed by any of a variety of deposition methods such as a PECVD method and a sputtering method. It is preferable that the insulating films 132 to 134 be formed in succession in a vacuum. In such a case, entry of impurities into each interface between the insulating films 132, 133, and 134 can be suppressed. In the case where the insulating film 132 and the insulating film 133 are formed using the same kind of material, the interface between the insulating film 132 and the insulating film 133 cannot be clearly defined in some cases.

For example, as the insulating film 132, a silicon oxide film or a silicon oxynitride film can be formed by a PECVD method under the following formation conditions. As for the formation conditions, the substrate is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., a deposition gas containing silicon and an oxidizing gas are introduced as a source gas into the treatment chamber, the pressure in the treatment chamber is greater than or equal to 20 Pa and less than or equal to 250 Pa, preferably greater than or equal to 40 Pa and less than or equal to 200 Pa, and high-frequency power is supplied to an electrode provided in the treatment chamber.

Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, nitrogen dioxide, or the like can be used.

By setting the ratio of the amount of the oxidizing gas to the amount of the deposition gas containing silicon to 100 or higher, the hydrogen content in the insulating film 132 can be reduced and dangling bonds in the insulating film 132 can be reduced. Oxygen released from the insulating film 133 is captured by the dangling bonds in the insulating film 132 in some cases; thus, in the case where the dangling bonds in the insulating film 132 are reduced, oxygen in the insulating film 133 can enter the semiconductor layer 120 efficiently to fill the oxygen vacancies in the semiconductor layer 120. As a result, the amount of hydrogen which enters the semiconductor layer 120 can be reduced and oxygen vacancies in the oxide semiconductor films can be reduced.

In the case where a silicon oxide film or a silicon oxynitride film is formed using a PECVD apparatus as the insulating film 133, the following formation conditions enables the oxygen concentration in the insulating film 133 to be increased. The source gases of the insulating films 133 (the insulating film 131) are similar to that of the insulating film 132.

The substrate is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C., preferably higher than or equal to 180° C. and lower than or equal to 230° C., a source gas is introduced into the treatment chamber, the pressure in the treatment chamber is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa, and high-frequency power that is higher than or equal to 0.17 W/cm² and lower than or equal to 0.5 W/cm², preferably higher than or equal to 0.25 W/cm² and lower than or equal to 0.35 W/cm² is supplied to an electrode provided in the treatment chamber.

During the formation of the insulating film 133, the high-frequency power having the density in the above range is supplied, whereby the decomposition efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas proceeds; therefore, the oxygen content in the insulating film 133 is higher than that in the stoichiometric composition. However, in the case where the substrate temperature is within the above temperature range, the bond between silicon and oxygen is weak, and accordingly, part of oxygen is released by heating. Thus, it is possible to form an oxide insulating film which contains oxygen at a higher proportion than the stoichiometric composition and from which part of oxygen is released by heating. Moreover, the insulating film 132 is provided over the semiconductor layer 120. Accordingly, in the process for forming the insulating film 133, the insulating film 132 serves as a protective film of the semiconductor layer 120. Thus, even when the insulating film 133 is formed using the high-frequency power having a high power density, damage to the semiconductor layer 120 can be suppressed.

By increasing the thickness of the insulating film containing oxygen such as a silicon oxide film, a larger amount of oxygen is released by heating; thus, the insulating film 133 is preferably formed thicker than the insulating film 132. Since the insulating film 132 is provided, favorable coverage can be achieved even when the insulating film 133 is formed thick.

For example, in the case where a silicon nitride film with a low hydrogen content is formed by a PECVD apparatus as the insulating film 134, the insulating film 134 can be formed under the following formation conditions. The substrate is held at a temperature higher than or equal to 80° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., the pressure is greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa with introduction of a source gas into the treatment chamber, and high-frequency power is supplied to an electrode provided in the treatment chamber.

As the source gas of the insulating film 134, a deposition gas containing silicon, a nitrogen gas, and an ammonia gas are preferably used. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Further, the flow rate of nitrogen is preferably 5 times to 50 times that of ammonia, further preferably 10 times to 50 times that of ammonia. The use of ammonia as the source gas facilitates decomposition of nitrogen and the deposition gas containing silicon. This is because ammonia is dissociated by plasma energy or heat energy, and energy generated by the dissociation contributes to decomposition of a bond of the deposition gas molecules containing silicon and a bond of nitrogen molecules. Under the above conditions, a silicon nitride film which has a low hydrogen content and can suppress entry of impurities such as hydrogen and water from the outside can be formed.

It is preferable that heat treatment be performed at least after formation of the insulating film 133 so that excess oxygen contained in the insulating film 132 or the insulating film 133 enters the semiconductor layer 120 to fill oxygen vacancies in the semiconductor layer 120. The heat treatment can be performed as heat treatment for dehydration or dehydrogenation of the semiconductor layer 120.

Through the above steps, the transistors in the pixel 31, the driver circuits 41 to 43 in the liquid crystal panel can be manufactured.

<Manufacture of Pixel Electrode and Common Electrode>

Next, steps of manufacturing the pixel electrode 116 and the common electrode 115 in the pixel 31 are described with reference to FIG. 3, FIG. 4, FIG. 5, and FIG. 6.

The organic resin film 135 is formed so as to cover the transistor. The organic resin film 135 is a base film of the common electrode 115 and the pixel electrode 116 and is formed as a planarization film for reducing unevenness due to the transistor, the wirings, and the like. For the organic resin film 135, an acrylic resin, a polyimide resin, or the like can be used.

A resist mask is formed over the organic resin film 135 by using a fourth photomask. By an etching step using this resist mask, a contact hole is formed through the insulating films 131 to 134 using inorganic materials and the organic resin film 135. The contact hole formed here is used to connect the wiring/electrode in the second layer over the insulating film 131 to a wiring/electrode formed over the organic resin film 135. For example, a contact hole for connecting the common electrode 115 to the wiring 117 over the insulating film 131 is also formed (see FIG. 6).

Although one more photomask is needed, a photomask for forming a contact hole in the organic resin film 135 and a photomask for forming a contact hole in the insulating films 131 to 134 can be used separately.

Next, a transparent conductive film is formed over the organic resin film 135. A resist mask is formed over the transparent conductive film by using a fifth photomask. The transparent conductive film is etched using this resist mask, so that the common electrode 115 is formed. Further, the electrode 162 in the terminal portion 60 in FIG. 2, the electrode 173 in FIG. 7, and the like are formed using the transparent conductive film.

As illustrated in FIG. 7, the wiring 171 in the first layer and the wiring 172 in the second layer are connected to each other through the electrode 173 in the third layer. Note that in a connection portion similar to that of FIG. 7, an electrode may be formed using the conductive film 301 or the conductive film 302.

In the case where the wiring 171 and the wiring 172 are connected to each other through the electrode 173 in the third layer as illustrated in FIG. 7, the number of photomasks can be reduced by one as compared to that in the case where a connection portion where the wiring 171 and the wiring 172 are directly connected to each other is formed. This is because a photomask for forming a contact hole in the insulating film 131 is needed before the conductive film 302 is formed in order to form a connection portion where the wiring 171 and the wiring 172 are directly connected to each other; on the other hand, the photomask is unnecessary in manufacture of the connection portion in FIG. 7.

The insulating film 136 is formed over the entire area of the substrate 100 so as to cover the common electrode 115. The insulating film 136 is formed as a passivation film for preventing entry of an impurity such as water from the outside. Further, the insulating film 136 forms a dielectric of the capacitor formed in the region where the common electrode 115 and the pixel electrode 116 overlap with each other. Like the insulating film 134, the insulating film 136 is preferably an insulating film of a nitride or a nitride oxide and for example, a silicon nitride film, a silicon nitride oxide film, or the like may be formed.

A resist mask is formed over the insulating film 136 by using a sixth photomask. The insulating film 136 is etched using this resist mask, so that at least a contact hole reaching the electrode 112 is formed.

A transparent conductive film is formed over the insulating film 136. A resist mask is formed over the transparent conductive film by using a seventh photomask. The transparent conductive film is etched using the resist mask, so that the pixel electrode 116 is formed. The pixel electrode 116 is connected to the electrode 112.

As the transparent conductive film included in the common electrode 115 and the pixel electrode 116, a film of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide, indium zinc oxide, indium tin oxide to which silicon oxide is added, or the like can be used. An alignment film 137 is formed over the substrate 100 in a cell process described below.

Here, a spacer 241 for keeping a cell gap is formed on the substrate 100 side. The spacer 241 formed of a resin is formed in each pixel by applying a photosensitive curable resin over the pixel electrode 116, exposing the resin to light through an eighth photomask, and performing development treatment.

<Manufacture of Color Filter, Black Matrix, and Spacer>

Here, the black matrix 210, the color filter 211, and the overcoat 212 are formed over the substrate 200. The black matrix 210 and the color filter 211 may be formed over the substrate 100. The spacer 241 for keeping a cell gap is formed on the substrate 200 side. Note that the spacer 241 may be formed on the substrate 100 side.

The spacer 241 is formed using a resin by applying a photosensitive curable resin over the overcoat 212, exposing the resin to light through an eighth photomask, and performing development treatment. An alignment film 213 is formed over the substrate 200 in a cell process described below.

<Cell Process>

A cell process is described below. The substrate 100 on which the display portion 30, the driver circuits 41 to 43, and the terminal portion 60 are formed (hereinafter referred to as a circuit board 100) and the substrate 200 over which the color filter 211 and the like are formed (hereinafter referred to as a color filter substrate 200) are bonded to each other with a liquid crystal material sealed therebetween, whereby the liquid crystal panel 10 is manufactured.

Entry of water causes variation in threshold voltage or the like of a transistor including an oxide semiconductor, and accordingly, the reliability of the transistor is decreased. Therefore, as described above, in a manufacturing process of the circuit board 100, it is preferable to perform successive film formation and removal of an impurity (treatment for highly purifying the oxide semiconductor) of an oxide semiconductor, such as heat treatment for dehydrogenation. In view of this, also in the cell process, it is preferable not to take an impurity, particularly moisture, in the liquid crystal panel. Since providing desiccant or the like as in an organic EL panel is difficult in a liquid crystal panel due to the existence of a liquid crystal material, it is preferable not to take moisture in the liquid crystal panel in the cell process. Further, since an organic resin film has a higher hygroscopic property than an inorganic insulating film, the water concentration in the organic resin film 135 easily increases between formation of the organic resin film 135 and the cell process. Performing the cell process in a situation where the circuit board 100 or the color filter substrate 200 contains much moisture causes decrease in the reliability of the liquid crystal panel.

In view of the above, in the cell process, drying treatment in order to remove moisture from the circuit board 100 or the color filter substrate 200 is performed, and the liquid crystal panel is manufactured in an atmosphere where moisture is not reattached. For example, the cell process is performed in an airtight treatment chamber. Further, heat treatment for removing moisture from the circuit board 100 and the color filter substrate 200 is performed at 100° C. or higher. The details of the cell process are described below.

<Formation of Alignment Film>

An alignment film 137 and the alignment film 213 are formed over the circuit board 100 and the color filter substrate 200, respectively. After the circuit board 100 is cleaned, a polyimide resin is applied over a surface of the circuit board 100 by a printing method or the like to form the alignment film 137 and baked, so that the alignment film 137 is formed. Alignment treatment is performed on the alignment film 137 through rubbing or irradiation with light. The alignment film 213 is similarly formed over the color filter substrate 200.

The following process is performed without exposure to the air in an airtight treatment chamber. The dew point of each treatment chamber is set to lower than or equal to −60° C., preferably lower than or equal to −75° C. For example, the dew point is set to about −80° C. to −60° C.

In other words, after all components are formed between the circuit board 100 and the substrate 200, the circuit board 100 and the color filter substrate 200 are always placed in a reduced pressure atmosphere with a dew point of −60° C. or lower, which contains little moisture, until the cell process ends. Note that when the treatment chamber is not set to reduced pressure, such as when the substrate is transferred, or the like, the atmosphere is set to an inert atmosphere such as a nitrogen atmosphere or an argon atmosphere.

<Drying Treatment>

The circuit board 100 and the color filter substrate 200 are subjected to drying treatment. As the drying treatment, heat treatment is performed under reduced pressure. The heating temperature is higher than or equal to 100° C., preferably higher than or equal to 150° C. The upper limit of the heating temperature depends on materials used for the circuit board 100 and the color filter substrate 200 and thus can be determined in consideration of the materials and the pressure at the time of pressure reduction. For example, the upper limit of the heating temperature can be 180° C. to 250° C. in the case where an acrylic resin is used as a resin material, and can be 250° C. to 300° C. in the case where a polyimide resin is used.

Further, the reduced pressure atmosphere has a pressure lower than the atmospheric pressure, preferably lower than or equal to 1 Pa, more preferably lower than or equal to 10⁻⁴ Pa. For example, the pressure of the treatment chamber is 1×10⁻⁴ Pa to 1×10⁻⁷ Pa.

<Application of Sealant and Dropping of Liquid Crystal>

Next, a sealant is applied over the color filter substrate 200 in order to seal the liquid crystal material. Here, an ultraviolet curable sealant for a one drop filling (ODF) method is applied. Next, the liquid crystal material is dropped in a region surrounded by the sealant on the color filter substrate 200. This step is performed in a nitrogen atmosphere.

<Bonding Step>

Next, the circuit board 100 and the color filter substrate 200 are transferred to a treatment chamber for bonding. The pressure of treatment chamber is reduced, and the circuit board 100 and the color filter substrate 200 are bonded to each other. Then, the circuit board 100 and the color filter substrate which are bonded to each other are transferred to another treatment chamber and the sealant is cured by irradiation with ultraviolet light, so that the sealing member 215 is finished. This step is performed in a nitrogen atmosphere, for example. The pressure in the treatment chamber can be 20 kPa to 0.1 Pa, preferably 100 Pa to 1 Pa.

Through the above cell process, a liquid crystal panel in which the liquid crystal layer 140 is sealed between the circuit board 100 and the color filter substrate 200 can be manufactured. By performing drying treatment (heat treatment) on the circuit board 100 and the color filter substrate 200 and controlling the atmosphere to keep a drying state of these substrates in the cell process, deterioration of the liquid crystal panel, which is caused by moisture, can be suppressed. Note that this will be described in Example 1.

By employing this embodiment, deterioration of a liquid crystal display device including an oxide semiconductor for a backplane (the circuit board 100), which is due to moisture, can be reduced. Accordingly, a highly reliable liquid crystal display device including an oxide semiconductor can be provided.

Further, by combination of a pixel structure of an FFS mode and a transistor including a crystalline oxide semiconductor film, a liquid crystal display device with high reliability, high definition, and low power consumption can be provided.

Thus, an FFS mode liquid crystal display device having a pixel aperture ratio of higher than or equal to 50% (preferably higher than or equal to 60%) and a resolution of higher than or equal to 300 dpi can be provided. For example, the liquid crystal panel having the specifications of FIG. 11 can be manufactured. FIG. 11 shows an example of a liquid crystal panel using an oxide semiconductor transistor.

Although an FFS mode pixel is described in this embodiment, the technique of this embodiment can employ other pixel structures such as a TN mode and the like while reducing driving voltage and increasing reliability.

This embodiment can be implemented combining with another embodiment as appropriate.

Embodiment 2

In this embodiment, a transistor included in the pixel 31 and the driver circuits 41 to 43 of the liquid crystal panel 10 is described.

<Semiconductor Layer 120>

As the oxide semiconductor used for the semiconductor layer 120 of a transistor, for example, any of the following can be used: indium oxide, tin oxide, zinc oxide, an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, an In—Ga-based oxide, an In—Ga—Zn-based oxide (also referred to as IGZO), an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, a Sn—Ga—Zn-based oxide, an Al—Ga—Zn-based oxide, a Sn—Al—Zn-based oxide, an In—Hf—Zn-based oxide, an In—Zr—Zn-based oxide, an In—Ti—Zn-based oxide, an In—Sc—Zn-based oxide, an In—Y—Zn-based oxide, an In—La—Zn-based oxide, an In—Ce—Zn-based oxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, an In—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide, an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-based oxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, an In—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, an In—Sn—Ga—Zn-based oxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, an In—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or an In—Hf—Al—Zn-based oxide.

For example, In—Ga—Zn-based oxide with an atomic ratio where In:Ga:Zn=1:1:1, In:Ga:Zn=3:1:2, or In:Ga:Zn=2:1:3, or an oxide whose composition is in the neighborhood of the above compositions can be used.

Further, when the oxide semiconductor film included in the semiconductor layer 120 contains a large amount of hydrogen, the hydrogen and an oxide semiconductor are bonded to each other, so that part of the hydrogen serves as a donor and causes generation of an electron which is a carrier. As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, it is preferable that, after formation of the oxide semiconductor film, dehydration treatment (dehydrogenation treatment) be performed to remove hydrogen and moisture from the oxide semiconductor film so that the oxide semiconductor film is highly purified to contain impurities as little as possible.

Note that oxygen in the oxide semiconductor film is also reduced by the dehydration treatment (dehydrogenation treatment) in some cases. Therefore, it is preferable that oxygen whose amount is reduced in the dehydration treatment (dehydrogenation treatment) be added to the oxide semiconductor or oxygen be supplied excessively to fill the oxygen vacancies in the oxide semiconductor film. In this specification and the like, supplying oxygen to the oxide semiconductor film may be expressed as oxygen adding treatment or oxygen supplying treatment.

In this manner, hydrogen or moisture is removed from the oxide semiconductor film by the dehydration treatment (dehydrogenation treatment) and oxygen vacancies therein are filled by the oxygen adding treatment, whereby the oxide semiconductor film can be turned into an i-type (intrinsic) or substantially i-type (intrinsic) oxide semiconductor film which is extremely close to an i-type oxide semiconductor film. Note that the substantially i-type oxide semiconductor means that the oxide semiconductor film includes extremely few (close to zero) carriers derived from a donor, and the carrier concentration thereof is lower than or equal to 1×10¹⁷/cm³, lower than or equal to 1×10¹⁶/cm³, lower than or equal to 1×10¹⁵/cm³, lower than or equal to 1×10¹⁴/cm³, or lower than or equal to 1×10¹³/cm³.

In this manner, the transistor including an i-type (intrinsic) or substantially i-type oxide semiconductor film can have extremely favorable off-state current characteristics. For example, the drain current at the time when the transistor including an oxide semiconductor film is in an off-state at room temperature (25° C.) can be less than or equal to 1×10⁻¹⁸ A, preferably less than or equal to 1×10⁻²¹ A, and further preferably 1×10⁻²⁴ A; or at 85° C., less than or equal to 1×10⁻¹⁵ A, preferably 1×10⁻¹⁸ A, further preferably less than or equal to 1×10⁻²¹ A. An off state of a transistor refers to a state where a gate voltage is much lower than a threshold voltage in an n-channel transistor. Specifically, when the gate voltage is lower than the threshold voltage by 1 V or more, preferably 2 V or more, more preferably 3 V or more, the transistor is turned off.

A structure of an oxide semiconductor film is described below.

An oxide semiconductor film may be a single-crystal oxide semiconductor film or a non-single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film includes any of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, a polycrystalline oxide semiconductor film, a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, and the like.

Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

An amorphous oxide semiconductor film is an oxide semiconductor film which has disordered atomic arrangement and no crystalline component. A typical example thereof is an oxide semiconductor film in which no crystal part exists even in a microscopic region, and the whole of the film is amorphous.

The microcrystalline oxide semiconductor film includes a microcrystal (also referred to as nanocrystal) with a size greater than or equal to 1 nm and less than 10 nm, for example. Thus, the microcrystalline oxide semiconductor film has a higher degree of atomic order than the amorphous oxide semiconductor film. Hence, the density of defect states of the microcrystalline oxide semiconductor film is lower than that of the amorphous oxide semiconductor film.

The CAAC-OS film is one of oxide semiconductor films including a plurality of crystal parts, and most of the crystal parts each fit inside a cube whose one side is less than 100 nm. Thus, there is a case where a crystal part included in the CAAC-OS film fits a cube whose one side is less than 10 nm, less than 5 nm, or less than 3 nm. The density of defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor film. The CAAC-OS film is described in detail below.

In the following description, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. In addition, a term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.

In a transmission electron microscope (TEM) image of the CAAC-OS film, a boundary between crystal parts, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

According to the TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology reflected by a surface over which the CAAC-OS film is formed (hereinafter, a surface over which the CAAC-OS film is formed is referred to as a formation surface) or a top surface of the CAAC-OS film, and is arranged in parallel to the formation surface or the top surface of the CAAC-OS film.

On the other hand, according to the TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (plan TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.

From the results of the cross-sectional TEM image and the plan TEM image, alignment is found in the crystal parts in the CAAC-OS film.

A CAAC-OS film is subjected to structural analysis with an X-ray diffraction (XRD) apparatus. For example, when the CAAC-OS film including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears frequently when the diffraction angle (2θ) is around 31°. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS film have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS film.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which an X-ray enters a sample in a direction substantially perpendicular to the c-axis, a peak appears frequently when 2θ is around 56°. This peak is derived from the (110) plane of the InGaZnO₄ crystal. Here, analysis (φ scan) is performed under conditions where the sample is rotated around a normal vector of a sample surface as an axis (φ axis) with 2θ fixed at around 56°. In the case where the sample is a single-crystal oxide semiconductor film of InGaZnO₄, six peaks appear. The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of a CAAC-OS film, a peak is not clearly observed even when 0 scan is performed with 2θ fixed at around 56°.

According to the above results, in the CAAC-OS film having c-axis alignment, while the directions of a-axes and b-axes are different between crystal parts, the c-axes are aligned in a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, each metal atom layer arranged in a layered manner observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.

Note that the crystal part is formed concurrently with deposition of the CAAC-OS film or is formed through crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is aligned with a direction parallel to a normal vector of a formation surface or a normal vector of a top surface. Thus, for example, in the case where a shape of the CAAC-OS film is changed by etching or the like, the c-axis might not be necessarily parallel to a normal vector of a formation surface or a normal vector of a top surface of the CAAC-OS film.

Further, the degree of crystallinity in the CAAC-OS film is not necessarily uniform. For example, in the case where crystal growth leading to the CAAC-OS film occurs from the vicinity of the top surface of the film, the degree of the crystallinity in the vicinity of the top surface is higher than that in the vicinity of the formation surface in some cases. Further, when an impurity is added to the CAAC-OS film, the crystallinity in a region to which the impurity is added is changed, and the degree of crystallinity in the CAAC-OS film varies depends on regions.

Note that when the CAAC-OS film with an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak of 2θ may also be observed at around 36°, in addition to the peak of 2θ at around 31°. The peak of 2θ at around 36° is derived from the (311) plane of a ZnGa₂O₄ crystal; such a peak indicates that a ZnGa₂O₄ crystal is included in part of the CAAC-OS film including the InGaZnO₄ crystal. It is preferable that in the CAAC-OS film, a peak of 2θ appear at around 31° and a peak of 2θ do not appear at around 36°.

In a transistor whose channel includes CAAC-OS, change in electric characteristics of the transistor due to irradiation with visible light or ultraviolet light is small. Thus, the transistor has stable electrical characteristics.

For the deposition of the CAAC-OS film, the following conditions are preferably used.

By increasing the substrate temperature during the deposition, migration of flat-plate-like sputtered particles which have reached the substrate occurs, so that a flat plane of the sputtered particles is attached to the substrate. At this time, the sputtered particles are positively charged, whereby the sputtered particles repelling each other are attached to the substrate. Therefore, the sputtered particles are not gathered and are not overlapped unevenly with each other, so that the CAAC-OS film having a uniform thickness can be formed. Specifically, the substrate temperature during the deposition is higher than or equal to 100° C. and lower than or equal to 740° C., preferably higher than or equal to 200° C. and lower than or equal to 500° C.

By reducing the amount of impurities entering the CAAC-OS film during the deposition, the crystal state can be prevented from being broken by the impurities. For example, the concentration of impurities (e.g., hydrogen, water, carbon dioxide, and nitrogen) which exist in the deposition chamber may be reduced. Furthermore, the concentration of impurities in a deposition gas may be reduced. Specifically, a deposition gas whose dew point is −80° C. or lower, preferably −100° C. or lower is used.

Furthermore, it is preferable that the proportion of oxygen in the deposition gas be increased and the power be optimized in order to reduce plasma damage at the deposition. The proportion of oxygen in the deposition gas is 30 vol % or higher, preferably 100 vol %.

After the CAAC-OS film is deposited, heat treatment may be performed. The temperature of the heat treatment is higher than or equal to 100° C. and lower than or equal to 740° C., preferably higher than or equal to 200° C. and lower than or equal to 500° C. Further, the heat treatment is performed for 1 minute to 24 hours, preferably 6 minutes to 4 hours. The heat treatment may be performed in an inert atmosphere or an oxidation atmosphere. It is preferable to perform heat treatment in an inert atmosphere and then to perform heat treatment in an oxidation atmosphere. The heat treatment in an inert atmosphere can reduce the concentration of impurities in the CAAC-OS film for a short time. At the same time, the heat treatment in an inert atmosphere may generate oxygen vacancies in the CAAC-OS film. In this case, the heat treatment in an oxidation atmosphere can reduce the oxygen vacancies. The heat treatment can further increase the crystallinity of the CAAC-OS film. Note that the heat treatment may be performed under a reduced pressure of 1000 Pa or less, 100 Pa or less, 10 Pa or less, or 1 Pa or less. The heat treatment under the reduced atmosphere can reduce the concentration of impurities in the CAAC-OS film for a shorter time.

The oxide semiconductor film 311 contains one or more kinds of elements contained in the oxide semiconductor film 312. The energy at the bottom of the conduction band of the oxide semiconductor film 311 is located closer to the vacuum level than that of the oxide semiconductor film 312 by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Note that the oxide semiconductor film 312 preferably contains at least indium because carrier mobility can be increased. When an electric field is applied to the gate electrode (scan line 110) of the transistor, a channel is formed in the oxide semiconductor film 312 of the multi-layer semiconductor layer 120, whose energy at the bottom of the conduction band is low.

That is, the oxide semiconductor film 311 is formed between the oxide semiconductor film 312 and the gate insulating film (insulating film 131), whereby a channel of the transistor can be formed in the oxide semiconductor film 312 which is not in contact with the insulating film 131. Further, since the oxide semiconductor film 311 contains one or more kinds of elements contained in the oxide semiconductor film 312, interface scattering is unlikely to occur at the interface between the oxide semiconductor films 312 and 311. Thus, the transistor can have a high field-effect mobility because the movement of carriers is not hindered at the interface.

For example, the oxide semiconductor film 311 may be an oxide film containing, for example, aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium at a higher atomic ratio than the oxide semiconductor film 312. Specifically, the amount of any of the above elements in the oxide semiconductor film 311 in an atomic ratio is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more as much as that in the oxide semiconductor film 312 in an atomic ratio. The above element is strongly bonded to oxygen, and thus has a function of suppressing generation of oxygen vacancies in the oxide film. That is, an oxygen vacancy is more unlikely to be generated in the oxide semiconductor film 311 than in the oxide semiconductor film 312.

Alternatively, when each of the oxide semiconductor film 311 and the oxide semiconductor film 312 is an In-M-Zn oxide and the oxide semiconductor film 311 and the oxide semiconductor film 312 contain In, m, and Zn in an atomic ratio of x₁:y₁:z₁ and an atomic ratio of x₂:y₂:z₂ respectively, y₁/x₁ needs to be larger than y₂/x₂. Note that the element M is a metal element whose bonding strength to oxygen is larger than that of In, and Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, and Hf can be given as examples. Preferably, the oxide semiconductor film 311 and the oxide semiconductor film 312 in which y₁/x₁ is 1.5 times or more as large as y₂/x₂ are selected. More preferably, the oxide semiconductor film 311 and the oxide semiconductor film 312 in which y₁/x₁ is twice or more as large as y₂/x₂ are selected. Still more preferably, the oxide semiconductor film 311 and the oxide semiconductor film 312 in which y₁/x₁ is three times or more as large as y₂/x₂ are selected. Here, in the oxide semiconductor film 312, y₁ is preferably larger than or equal to x₁ because the transistor can have stable electrical characteristics. However, when y₁ is three times or more as large as x₁, the field-effect mobility of the transistor is reduced; accordingly, y₁ is preferably equal to x₁ or smaller than three times x₁.

The thickness of the oxide semiconductor film 311 is greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm. The thickness of the oxide semiconductor film 312 is greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

The oxide semiconductor film 313 is an oxide film which contains one or more kinds of elements contained in the oxide semiconductor film 312. The energy at the bottom of the conduction band of the oxide semiconductor film 313 is located closer to the vacuum level than that of the oxide semiconductor film 312 by 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. Since the oxide semiconductor film 313 contains one or more kinds of elements contained in the oxide semiconductor film 312, an interface state is unlikely to be formed at the interface between the oxide semiconductor film 312 and the oxide semiconductor film 313. When the interface has an interface state, in some cases, a second transistor in which the interface serves as a channel and which has a different threshold voltage is formed; accordingly, the apparent threshold voltage of the transistor is changed. Thus, with the oxide semiconductor film 313, fluctuation in electrical characteristics of the transistors, such as a threshold voltage, can be reduced.

The oxide semiconductor film 313 may be, for example, an oxide film containing aluminum, silicon, titanium, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, or hafnium at a higher atomic ratio than the oxide semiconductor film 312. Specifically, as the oxide semiconductor film 313, an oxide film containing the above element in an atomic ratio 1.5 times or more, preferably twice or more, more preferably three times or more that in the oxide semiconductor film 312 is used. The above element is strongly bonded to oxygen, and thus has a function of suppressing generation of oxygen vacancies in the oxide film. That is, an oxygen vacancy is more unlikely to be generated in the oxide semiconductor film 313 than in the oxide semiconductor film 312.

Further alternatively, when each of the oxide semiconductor film 312 and the oxide semiconductor film 313 is an In-M-Zn oxide and the oxide semiconductor film 312 and the oxide semiconductor film 313 contain In, m, and Zn in an atomic ratio of x₂:y₂:z₂ and an atomic ratio of x₃:y₃:z₃ respectively, y₃/x₃ needs to be larger than y₂/x₂. Note that the element M is a metal element whose bonding strength to oxygen is larger than that of In, and Al, Ti, Ga, Y, Zr, Sn, La, Ce, Nd, and Hf can be given as examples. Preferably, the oxide semiconductor film 312 and the oxide semiconductor film 313 in which y₃/x₃ is 1.5 times or more as large as y₂/x₂ are selected. More preferably, the oxide semiconductor film 312 and the oxide semiconductor film 313 in which y₃/x₃ is twice or more as large as y₂/x₂ are selected. Still more preferably, the oxide semiconductor film 312 and the oxide semiconductor film 313 in which y₃/x₃ is three times or more as large as y₂/x₂ are selected. Here, in the oxide semiconductor film 312, y₂ is preferably larger than or equal to x₂ because the transistor can have stable electrical characteristics. However, when y₂ is three times or more as large as x₂, the field-effect mobility of the transistor is reduced; accordingly, y₂ is preferably equal to x₂ or smaller than three times x₂.

The thickness of the oxide semiconductor film 313 is greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm.

In the semiconductor layer 120 having a three-layer structure, the oxide semiconductor films 311, 312, and 313 each are amorphous or crystalline. It is preferable that the oxide semiconductor film 311 be amorphous, the oxide semiconductor film 312 be crystalline, and the oxide semiconductor film 313 be amorphous or crystalline. Since the oxide semiconductor film 312 where a channel is formed has a crystalline structure, a transistor can have stable electrical characteristics.

<Method for Forming Oxide Semiconductor Film>

An example of a method for forming the oxide semiconductor films 311 to 313 by a sputtering method using an In—Ga—Zn oxide film is described below.

For deposition of the oxide semiconductor films 311 and 313, a sputtering target of an In—Ga—Zn oxide (In:Ga:Zn=1:3:2 [atomic ratio]) can be used. The deposition conditions can be as follows: an argon gas (flow rate: 30 sccm) and an oxygen gas (flow rate: 15 sccm) are used as the deposition gas; the pressure is 0.4 Pa; the substrate temperature is 200° C.; and the DC power is 0.5 kW.

The CAAC-OS film is used as the oxide semiconductor film 312. Thus, a sputtering target of an In—Ga—Zn oxide (In:Ga:Zn=1:1:1 [atomic ratio]) which is polycrystalline is preferably used for the deposition. The deposition conditions can be as follows: an argon gas (flow rate: 30 sccm) and an oxygen gas (flow rate: 15 sccm) are used as the deposition gas; the pressure is 0.4 Pa; the substrate temperature is 300° C.; and the DC power is 0.5 kW.

The transistor including the semiconductor layer 120 formed in the above-described manner has stable electrical characteristics and a high field-effect mobility because the channel is formed in the oxide semiconductor film 312.

Entry of impurities such as water causes variation in threshold voltage or the like of a transistor including an oxide semiconductor, and accordingly, the reliability of the transistor is decreased. Therefore, as described in Embodiment 1, in a manufacturing process of the circuit board 100, it is preferable to perform successive film formation and removal of an impurity (treatment for highly purifying the oxide semiconductor) of an oxide semiconductor, such as heat treatment for dehydrogenation.

Various experiments can prove low off-state current of a transistor in which a purified oxide semiconductor is used. For example, even when an element has a channel width (W) of 1×10⁶ μm and a channel length (L) of 10 μm, off-state current was less than or equal to the measurement limit of a semiconductor parameter analyzer at a voltage (drain voltage) between the source electrode and the drain electrode of from 1 V to 10 V. The measurement results suggest that the off-state current of the transistor is 1×10⁻¹³ A or lower. In this case, the off-state current corresponding to a value obtained by dividing the off-state current by the channel width of the transistor is 100 zA/μm or lower.

Further, the off-state current was measured with the use of a circuit in which a capacitor and a transistor are connected to each other and charge that flows in the capacitor or flows out from the capacitor is controlled by the transistor. For the measurement, the transistor in which a channel formation region is formed in a purified oxide semiconductor film was used, and the off-state current of the transistor was measured from a change in the amount of charge of the capacitor per unit time. As a result, it is found that in the case where the voltage between the source electrode and the drain electrode of the transistor is 3 V, lower off-state current of several tens of yoctoamperes per micrometer (yA/μm) can be obtained. With the use of a purified oxide semiconductor, the off-state current of the transistor can be significantly reduced.

Therefore, the transistor 35 of the pixel 31 including an oxide semiconductor in the semiconductor layer has an electric characteristic of extremely small off-state current. With the use of a transistor with extremely small off-state current as the switching element of the pixel 31, variation in the potential corresponding to the data signal written to the pixel electrode 116 due to the off-state current can be reduced.

Thus, in the pixel 31, the capacitance of the capacitor C1 including the pixel electrode 116, the insulating film 136, and the common electrode 115 can be smaller that than in a pixel in which a transistor using silicon is used for a switching element of the pixel (see FIG. 4 and FIG. 10A). As the area of the region where the pixel electrode 116 and the common electrode 115 overlap with each other increases, the capacitance of the capacitor C1 becomes larger, whereas the capacitance of the capacitor C1 can be smaller as the area of the region where the pixel electrode 116 and the common electrode 115 overlap with each other decreases; thus, the transmittance of the pixel 31 can be increased. When the transmittance is increased, luminance of a backlight can be reduced, so that the power consumption of the liquid crystal display device can be reduced.

In addition, since variation in the potential corresponding to the data signal written to the pixel electrode 116 can be suppressed, in a period for displaying an image with no motion such as a still image, rewriting of data of the pixel 31 is not needed in every frame period, i.e., rewiring of data is not needed for two frame periods or more. A method for driving such a liquid crystal display device will be described in detail in Embodiment 4. By reducing times of rewriting, power consumption by rewriting can be reduced.

This embodiment can be implemented combining with another embodiment as appropriate.

Embodiment 3

The liquid crystal panel 10 in FIG. 1 provided with a touch sensor (contact detector) can function as a touch panel.

In this embodiment, a touch panel is described with reference to FIG. 12, FIG. 13, and FIGS. 14A and 14B.

FIG. 12 is a cross-sectional view illustrating a structural example of a touch panel 400 using the liquid crystal panel 10. FIG. 13 is a plan view illustrating a structural example of the common electrode 421 and the electrode 422 of the touch panel 400. FIG. 14A is a cross-sectional view taken along line C1-C2 in FIG. 13, and FIG. 14B is a plan view of a region 240 in FIG. 13.

The touch panel 400 includes a capacitive sensor as a touch sensor. A polarizing plate 411 is attached to the outer side of the substrate 100, and a polarizing plate 412 is attached to the outer side of the substrate 200.

A common electrode 421 over the substrate 100 serves as a common electrode of a pixel and an electrode of a capacitor in the touch sensor. The electrode 422 is provided between the substrate 200 and the polarizing plate 412. The electrode 422 serves as an electrode of a capacitor in the touch sensor. Further, since the liquid crystal panel 10 has a pixel structure of an FSS-mode, a conductive film is not formed on the substrate 200 side; thus, the electrode 422 functions as an antistatic conductor for the substrate 200.

The common electrode 421 and the electrode 422 each have a stripe shape and are provided so as to be perpendicular to each other on a plane. Each common electrode 421 is connected to an FPC 461 attached to the substrate 100 through a lead wiring 431, and each electrode 422 is connected to an FPC 462 attached to the substrate 200 through a lead wiring 432. As shown in FIG. 14A, the common electrode 421 is shared among the plurality of pixels, and the pixel electrode 116 is provided in each of the pixels and connected to the transistor 35.

Capacitance of the touch sensor is formed in the region where the common electrode 421 and the electrode 422 intersect with each other. In the capacitor including the common electrode 421 and the electrode 422 as a pair of electrodes, the common electrode 421 is an electrode for supplying a potential to the capacitor. The electrode 422 is an electrode for obtaining current flowing through the capacitor.

Operations of the touch panel 400 can be broadly classified into two operations: a display operation of inputting a video signal to the pixel and a sensing operation of detecting contact. In the display operation, the potential of the common electrode 421 is fixed at a low level. During a sensing period, pulse signals are sequentially applied to the common electrodes 421 and thus, the potentials of the common electrodes are set at a high level. At this time, when a finger touches the touch panel 400, capacitance due to the finger is applied to the capacitor of the touch sensor; thus, current flowing through the capacitor is changed, so that the potential of the electrode 422 is changed. The electrodes 422 are sequentially scanned and a change in the potential of the electrode 422 is detected, so that a position which is touched by the finger is detected.

As described above, when the touch panel is formed using the liquid crystal panel 10, the antistatic conductor originally provided in the FSS-mode liquid crystal panel 10 and the common electrode of the pixel can be used as electrodes forming capacitance of the touch panel 400; thus, a touch panel that is thin and lightweight and has high display quality can be provided.

Although the common electrode 421 is provided below the pixel electrode 116 (on the board 100 side), the common electrode 421 may be provided over the pixel electrode 116.

Note that the structure of a touch panel using a liquid crystal panel can be a structure other than the touch panel 400 described in this embodiment. For example, an external touch panel in which electrostatic capacitance is formed and a touch panel substrate is provided on the substrate 200 side of the liquid crystal panel 10 can be used. Alternatively, with the use of an antistatic conductive film attached outside the substrate 200 of the liquid crystal panel 10, a surface capacitive touch sensor can be formed. A structural example of a touch sensor used for an external touch panel will be described with reference to FIG. 15, FIG. 16, FIG. 17, and FIG. 18.

FIG. 15A is a perspective exploded view illustrating a structural example of a touch sensor, and FIG. 15B is a plan view illustrating a structural example of an electrode of the touch sensor. FIG. 16 is a cross-sectional view of a structural example of the touch sensor 450.

The touch sensor 450 illustrated in FIG. 15A and FIG. 15B includes, over a substrate 491, the plurality of electrodes 451 arranged in an X-axis direction and the plurality of electrodes 452 arranged in a Y-axis direction which intersects with the X-axis direction.

The plurality of electrodes 451 and the plurality of electrodes 452 each have a shape in which a plurality of rectangular conductive films is connected to each other. The plurality of electrodes 451 and the plurality of electrodes 452 are provided so that the positions of the rectangular conductive films of the electrodes 451 are different from those of the rectangular conductive films of the electrodes 452. In the portion where the electrode 451 and the electrode 452 intersect with each other, an insulating film is provided between the electrodes 451 and 452 so that the electrodes are not in contact with each other.

FIG. 16 illustrates an example of a cross-sectional view of a portion where the electrode 451 and the electrode 452 intersect with each other. FIG. 17 is an equivalent circuit diagram of a portion where the electrode 451 and the electrode 452 intersect with each other. As illustrated in FIG. 17, a capacitor 454 is formed in the portion where the electrodes 451 and 452 intersect with each other.

As shown in FIG. 16, the electrode 451 includes the conductive film 451 a and the conductive film 451 b in the first layer and the conductive film 451 c in the second layer over the insulating film 481. The conductive film 451 a and the conductive film 451 b are connected by the conductive film 451 c. The electrode 452 is formed using the same film as the conductive films 451 a and 451 b in the first layer. The insulating film 482 is formed to cover the electrodes 451, 452, and 471. As the insulating films 481 and 482, a silicon oxynitride film may be formed, for example. Note that a base film of an insulating film may be formed between the substrate 491 and the electrodes 451 and 471. As the base film, a silicon oxynitride film may be formed, for example.

The electrode 451 and the electrode 452 are formed using conductive materials having a property of transmitting visible light, such as indium tin oxide including silicon oxide, indium tin oxide, zinc oxide, indium zinc oxide, and zinc oxide to which gallium is added, for example.

The conductive film 451 a is connected to the electrode 471. The electrode 471 serves as a connection terminal with an FPC. Similarly to the electrode 451, the electrode 452 is connected to the electrode 471. The electrode 471 can be formed of a tungsten film, for example.

The insulating film 482 is formed to cover the electrodes 451, 452, and 471. An opening for electrically connecting the electrode 471 and the FPC is formed in the insulating films 481 and 482 over the electrode 471. The substrate 492 is bonded over the insulating film 482 with an adhesive, an adhesive film, or the like. The substrate side 491 is bonded to the color filter substrate of the liquid crystal panel with an adhesive or an adhesive film, so that a touch panel is completed.

FIG. 18 illustrates a mask pattern (layout) of a touch sensor 450 actually designed by a CAD. The touch sensor 450 in FIG. 18 is designed to be mounted on the liquid crystal panel in FIG. 11. The number of sensors is 18×12=216.

This embodiment can be implemented combining with another embodiment as appropriate.

Embodiment 4

In this embodiment, a driving method for reducing power consumption of a liquid crystal display device is described. By the driving method in this embodiment, power consumption of a liquid crystal display device including an oxide semiconductor transistor in a pixel can be further reduced. Reduction in power consumption of the liquid crystal display device is described with reference to FIG. 19 and FIG. 20.

FIG. 19 is a block diagram illustrating a structural example of a liquid crystal display device in this embodiment. As illustrated in FIG. 19, a liquid crystal display device 500 includes a liquid crystal panel 501 as a display module and a control circuit 510. The liquid crystal panel 501 corresponds to the liquid crystal panel 10 in FIG. 1.

An image signal (Video), which is digital data, and a synchronization signal (SYNC) for controlling rewriting of a screen of the liquid crystal panel 501 are input to the liquid crystal display device 500. Examples of a synchronization signal include a horizontal synchronization signal (Hsync), a vertical synchronization signal (Vsync), and a reference clock signal (CLK).

The liquid crystal panel 501 includes a display portion 530, a scan line driver circuit 540, and a data line driver circuit 550. The display portion 530 corresponds to the display portion 30 in FIG. 1 and includes a plurality of pixels 31. The pixels 31 in the same row are connected to the scan line driver circuit 540 through a common scan line 541, and the pixels 31 in the same column are connected to the data line driver circuit 550 through a common data line 551.

A high power supply voltage (VDD) and a low power supply voltage (VSS), which serve as power supply voltages, and a common voltage (Vcom) are supplied to the liquid crystal panel 501. The common voltage (hereinafter referred to as Vcom) is supplied to each pixel 31 in the display portion 530.

The data line driver circuit 550 processes an input image signal to generate a data signal, and outputs the data signal to the data line 551. The scan line driver circuit 540 outputs, to the scan line 541, a scan signal for selecting the pixel 31 into which a data signal is to be written.

The pixel 31 includes a switching element whose electrical connection to the data line 551 is controlled by a scan signal. When the switching element is turned on, a data signal is written into the pixel 31 through the data line 551.

The pixel 31 has a structure similar to the pixel 31 in FIG. 10B. An electrode to which Vcom is applied corresponds to the common electrode 115.

The control circuit 510 controls the whole liquid crystal display device 500 and includes a circuit which generates control signals for circuits included in the liquid crystal display device 500.

The control circuit 510 includes a control circuit generation circuit which generates control signals for the scan line driver circuit 540 and the data line driver circuit 550 on the basis of the synchronization signal (SYNC). Examples of a control signal for the scan line driver circuit 540 include a start pulse (GSP) and a clock signal (GCLK). Examples of a control signal for the data line driver circuit 550 include a start pulse (SSP) and a clock signal (SCLK). For example, the control circuit 510 generates a plurality of clock signals with the same cycle and shifted phases as the clock signals (GCLK and SCLK).

Further, the control circuit 510 controls output of an image signal (Video), which is input from the outside of the liquid crystal display device 500, to the data line driver circuit 550.

The data line driver circuit 550 includes a digital/analog conversion circuit 552 (hereinafter referred to as D-A conversion circuit 552). The D-A conversion circuit 552 converts an image signal to an analog signal, thereby generating a data signal.

Note that in the case where an image signal input to the liquid crystal display device 500 is an analog signal, the image signal is converted to a digital signal in the control circuit 510 and output to the liquid crystal panel 501.

An image signal is image data for each frame. The control circuit 510 has a function of performing image processing on the image signal and controlling output of the image signal to the data line driver circuit 550 on the basis of data obtained by the processing. For that function, the control circuit 510 includes a motion detection portion 511 which performs image processing on the image signal to detect motion in the image data for each frame. The control circuit 510 stops output of an image signal to the data line driver circuit 550 when the motion detection portion 511 determines that there is no motion, and restarts the output of an image signal when the motion detection portion 511 determines that there is motion.

There is no particular limitation on the image processing for detecting motion which is performed in the motion detection portion 511. An example of a method for detecting motion is to obtain difference data from image data for two consecutive frames. It can be determined whether there is motion or not from the obtained difference data. Another example of the method is to detect a motion vector.

In addition, the liquid crystal display device 500 may be provided with an image signal correction circuit which corrects an input image signal. For example, an image signal is corrected such that a voltage higher than a voltage corresponding to the gray level of the image signal is written into the pixel 31. Such correction can shorten the response time of the liquid crystal element 36. A method in which the control circuit 510 is driven with an image signal corrected in this manner is referred to as overdriving. In the case of performing high frame rate driving in which the liquid crystal display device 500 is driven at an integral multiple of the frame frequency of an image signal, image data for interpolation between two frames or image data for performing black display between two frames may be generated in the control circuit 510.

Next, the operation of the liquid crystal display device 500 for displaying an image with motion, such as a moving image, and an image without motion, such as a still image, is described with reference to a timing chart of FIG. 20. FIG. 20 shows the signal waveforms of a vertical synchronization signal (Vsync) and a data signal (Vdata) output to the data line 551 from the data line driver circuit 550.

FIG. 20 is a timing chart of the liquid crystal display device 500 during 3 m frame periods. Here, there is motion in image data in the first k frame periods and the last j frame periods and there is no motion in image data in the other frame periods. Note that k and j are each an integer greater than or equal to 1 and less than or equal to m−2.

In the first k frame periods, the motion detection portion 511 determines that there is motion in image data for each frame. The control circuit 510 outputs data signals (Vdata) to the data line 551 on the basis of the result of determination by the motion detection portion 511.

The motion detection portion 511 performs image processing for detecting motion and determines that there is no motion in image data for the (k+1)-th frame. Then, the control circuit 510 stops output of image signals (Video) to the data line driver circuit 550 in the (k+1)-th frame period on the basis of the result of determination by the motion detection portion 511. Thus, output of data signals (Vdata) from the data line driver circuit 550 to the data line 551 is stopped. Further, the control circuit 510 stops output of control signals (e.g., a start pulse signal and a clock signal) to the scan line driver circuit 540 and the data line driver circuit 550 in order to stop rewriting of data of the display portion 530. The control circuit 510 does not output an image signal to the data line driver circuit 550 nor output control signals to the scan line driver circuit 540 and the data line driver circuit 550, thereby keeping rewriting of data stopped, until the motion detection portion 511 determines that there is motion in image data.

Note that, in this specification, “to stop output of a signal” or “not to output a signal” means to apply voltage which is different from a predetermined voltage for operating a circuit to a wiring for supplying the signal, or to bring the wiring into an electrically floating state.

When rewriting of data of the display portion 530 is stopped, an electric field in one direction is kept applied to the liquid crystal element 36, which might lead to deterioration of liquid crystal in the liquid crystal element 36. In order to avoid such a problem, it is preferable that signals be supplied to the scan line driver circuit 540 and the data line driver circuit 550 from the control circuit 510 and data signals with an inverted polarity be written into the data line 551 at predetermined timings to invert the direction of the electric field applied to the liquid crystal element 36, regardless of the result of determination by the motion detection portion 511.

Note that the polarity of a data signal input to the data line 551 is determined relative to Vcom. The polarity is positive when the voltage of the data signal is higher than Vcom, and is negative when the voltage of the data signal is lower than Vcom.

Specifically, as shown in FIG. 20, in the (m+1)-th frame period, the control circuit 510 outputs control signals to the scan line driver circuit 540 and the data line driver circuit 550 and outputs an image signal (Video) to the data line driver circuit 550. The data line driver circuit 550 outputs a data signal (Vdata) with a polarity opposite to that of a data signal (Vdata) output to the data line 551 in the k-th frame period to the data line 551. In this manner, a data signal (Vdata) with an inverted polarity is written into the data line 551 in the (m+1)-th frame period and in the (2 m+1)-th frame period, which are periods in which no motion is detected in image data. Rewriting of data of the display portion 530 is intermittently performed in periods in which there is no change in image data; thus, it is possible to reduce power consumption due to rewriting and prevent deterioration of the liquid crystal element 36.

When the motion detection portion 511 determines that there is motion in image data for any frame after the (2 m+1)-th frame, the control circuit 510 controls the scan line driver circuit 540 and the data line driver circuit 550 to perform rewriting of data of the display portion 530.

As described above, with the driving method in FIG. 20, the polarity of a data signal (Vdata) is inverted every m frame periods regardless of whether there is motion in image data or not (Video). Meanwhile, data of the display portion 530 is rewritten every frame in periods in which an image with motion is displayed and is rewritten every m frames in periods in which an image without motion is displayed. Consequently, power consumed owing to rewriting of data can be reduced. This can prevent an increase in power consumption due to an increase in driving frequency and the number of pixels.

As described above, in the liquid crystal display device 500, the method for driving the liquid crystal display device is switched depending on a moving image display mode or a still image display mode; thus, it is possible to provide a liquid crystal display device with low power consumption while preventing deterioration of liquid crystal and maintaining display quality.

In the case of rewriting data of a pixel every one frame when displaying a still image, human eyes may perceive a flicker, which causes eyestrain. In the liquid crystal display device of this embodiment, the frequency of writing image signals is reduced in a still-image displaying period, whereby there is an advantageous effect of making eyestrain less severe.

Therefore, with the use of a liquid crystal panel whose backplane is formed using an oxide semiconductor including a crystal part, small-and-medium-sized liquid crystal display devices which are appropriate for a portable electronic appliance and is high-definition and low-power-consumption can be provided.

Note that, in order to prevent deterioration of the liquid crystal, the interval between polarity inversions of data signals (here, m frame periods) is set to two seconds or shorter, preferably one second or shorter.

Although the detection of motion in image data is performed in the motion detection portion 511 in the control circuit 510, the detection of motion is not necessarily performed only in the motion detection portion 511. Data on whether there is motion or not may be input to the control circuit 510 from the outside of the liquid crystal display device 500.

Determination that there is no motion in image data is not always based on image data for two consecutive frames; the number of frames required for the determination may be set as appropriate depending on the usage mode of the liquid crystal display device 500. For example, rewriting of data of the display portion 530 may be stopped when there is no motion in image data for m consecutive frames.

Embodiment 5

As described above, with the use of a liquid crystal panel whose backplane is formed using an oxide semiconductor including a crystal part, a liquid crystal display devices which is high-definition and low-power-consumption can be provided. Thus, such a liquid crystal display device meets the requirements of small-and-medium-sized liquid crystal display devices of a portable electronic appliance to which electric power cannot be easily supplied constantly, such as a portable information terminal or a portable game machine.

For example, the electronic device provided with a liquid crystal display device in a display portion can be used for display devices, laptops, or image reproducing devices provided with recording media (typically devices which reproduce the content of recording media such as DVDs (digital versatile disc) and have displays for displaying the reproduced images). Other examples are mobile phones, portable game consoles, personal digital assistants, e-book readers, cameras (such as video cameras and digital still cameras), goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines. FIGS. 21A to 21F each illustrate specific examples of these electronic devices.

FIG. 21A illustrates a portable game machine 700, which includes a housing 701, a housing 702, a display portion 703, a display portion 704, a microphone 705, speakers 706, a control key 707, a stylus 708, and the like. The touch panel 400 of Embodiment 2 is employed as the display portion 703 or 704. Alternatively, a touch panel including the touch sensor 450 and the liquid crystal panel may be employed as the display portion 703 or 704.

A video camera 710 in FIG. 21B includes a housing 711, a housing 712, a display portion 713, operation keys 714, a lens 715, a joint 716, and the like. The operation keys 714 and the lens 715 are provided in the housing 711, and the display portion 713 is provided in the housing 712. The housing 711 and the housing 712 are connected to each other with the joint 716, and an angle between the housing 711 and the housing 712 can be changed with the joint 716. An image on the display portion 713 may be switched depending on the angle between the housing 711 and the housing 712 at the joint 716. The liquid crystal panel 10 and the touch panel 400 can be used for the display portion 713. The touch sensor 450 or a touch panel including the liquid crystal panel can be used as the display portion 713.

A portable information terminal 720 in FIG. 21C includes a display portion 722 incorporated in a housing 721, an operation button 723, and a speaker 724. Further, although not shown, the portable information terminal 720 includes a microphone, a stereo headphone jack, a memory card insertion slot, a camera, an external connection port such as a USB connector, and the like.

A portable information terminal 730 shown in FIG. 21D includes a housing 731, a housing 732, a display portion 733, a display portion 734, a connection portion 735, an operation key 736, and the like. The liquid crystal panel 10 and the touch panel 400 can be used for the display portions 733 and 734. The touch sensor 450 or a touch panel including the liquid crystal panel can be used as the display portions 733 and 734.

The display portion 733 and the display portion 734 are provided in the housing 731 and the housing 732, respectively. The housing 731 and the housing 732 are connected to each other with the connection portion 735, and an angle between the housing 731 and the housing 732 can be changed with the connection portion 735. An image on the first display portion 733 may be switched depending on the angle between the housing 731 and the housing 732.

The liquid crystal panel 10 and the touch panel 400 can be used for the display portions 733 and 734. The touch panel 400 with a position input function or a touch panel including the touch sensor 450 and the liquid crystal panel is preferably used as at least one of the display portion 733 and the display portion 734.

A smartphone 740 shown in FIG. 21E includes a housing 741, a button 742, a microphone 743, a display portion 744, a speaker 745, a camera lens 746, and the like. Since the camera lens 746 is provided on the same plane as the display portion 744, videophone is possible. Since the display portion 744 includes the touch panel 400 or a touch panel including the touch sensor 450 and the liquid crystal panel, the smartphone 740 can be operated by a finger or the like. The display portion 744 changes the direction for displaying depending on a usage pattern.

A laptop personal computer 750 in FIG. 21F includes a housing 751, a display portion 752, a keyboard 753, a pointing device 754, and the like. The liquid crystal panel 10 is used as the display portion 752. The touch panel 400 or a touch panel including the touch sensor 450 and a liquid crystal panel may be used as the display portion 752.

This embodiment can be combined with any of the other embodiments as appropriate.

Example 1

Effects of the drying treatment and the atmosphere control in the cell process as described in Embodiment 1 are described. In order to confirm the effects, results of examining the amount of moisture released from a circuit board used for a liquid crystal panel by thermal desorption spectroscopy (TDS) are described below.

<TDS Measurement>

First, seven circuit boards A to G which were used for the TDS are described.

The circuit boards A to D were totally formed in the same process up to and including formation of the alignment film. Further, in each of the circuit boards A to D, a 3-μm-thick organic resin film including an acrylic resin is formed between a transistor and a pixel electrode. The circuit board A was not subjected to heat treatment after formation of the alignment film. The circuit board B was subjected to heat treatment at 160° C. for one hour in a reduced pressure atmosphere of about 1×10⁻⁵ Pa after formation of the alignment film. The circuit board C was subjected to heat treatment at 150° C. for six hours in an air atmosphere after formation of the alignment film. The circuit board D was subjected to heat treatment at 160° C. for one hour in a reduced pressure atmosphere of about 1×10⁻⁵ Pa and then was exposed to an air atmosphere for ten minutes.

The circuit boards E to G were totally formed in the same process up to and including formation of the alignment film. The circuit boards E to G each have a structure in which an organic resin film including an acrylic resin is not provided between a transistor and a pixel electrode and a pixel electrode is provided over an inorganic insulating film that covers the transistor. The circuit board E was not subjected to heat treatment after formation of the alignment film. The circuit board F was subjected to heat treatment at 160° C. for one hour in a reduced pressure atmosphere of about 1×10⁻⁵ Pa after formation of the alignment film. The circuit board G was subjected to heat treatment at 150° C. for six hours in an air atmosphere after formation of the alignment film.

In the TDS, the temperature of each board was raised from 60° C. to 230° C. at a speed of 20° C. per minute and the number of released gas molecules having a mass-to-charge ratio (m/z) of 18 was measured. Note that it is expected that the gas molecules having a mass-to-charge ratio (m/z) of 18 mainly include water. Further, an atmospheric pressure at the beginning of the measurement in a measurement chamber in which the circuit board was placed was 1.2×10⁻⁷ Pa.

FIG. 22 and FIG. 23 show TDS measurement results of the circuit boards A to D and TDS measurement results of the circuit boards E to G, respectively, which show change in intensities of gas molecules which have a mass-to-charge ratio (m/z) of 18 with respect to heating temperatures.

As shown in FIG. 22, the circuit board A which was not subjected to heat treatment has a peak showing release of water at a substrate temperature around 90° C. On the other hand, unlike the circuit board A, the circuit board B which was subjected to heat treatment in a reduced pressure atmosphere does not have a peak showing release of water at a substrate temperature around 90° C.

When the circuit board B which was subjected to heat treatment in a reduced pressure atmosphere is compared with the circuit board C which was subjected to heat treatment in an air atmosphere, the circuit board B has higher intensity showing release of water than the circuit board C at substrate temperatures of 160° C. or less. Thus, it is expected that the amount of water included in each film included in the circuit board B which was subjected to heat treatment in a reduced pressure atmosphere is smaller than that in the circuit board C which was subjected to heat treatment in an air atmosphere.

Further, the circuit board D which was exposed to an air atmosphere after heat treatment in a reduced pressure atmosphere has a peak showing release of water at a substrate temperature around 80° C. When the circuit board B which was subjected to heat treatment in a reduced pressure atmosphere is compared with the circuit board D which was exposed to an air atmosphere after the heat treatment in a reduced pressure atmosphere, it is expected that the amount of water included in each film included in the circuit board D is larger than that in the circuit board B.

When the intensity showing release of water of the circuit board A including the organic resin film, which is shown in FIG. 22, is compared with that of the circuit board E not including the organic resin film, which is shown in FIG. 23, it is found that the intensity showing release of water of the circuit board A is higher than that of the circuit board E in all the temperature ranges. Thus, as for the circuit boards A and E each of which was not subjected to heat treatment after formation of the alignment film, it can be considered that more water is released from the circuit board A including the organic resin film and that difference in the amount of released water is caused by water included in the organic resin film.

When the intensity showing release of water of the circuit board C including the organic resin film, which is shown in FIG. 22, is compared with that of the circuit board F not including the organic resin film, which is shown in FIG. 23, it is found that the intensity of the circuit board C is higher than that of the circuit board F in all the temperature ranges. Thus, as for the circuit boards C and G each of which was subjected to heat treatment in an air atmosphere after formation of the alignment film, it can be considered that more water is released from the circuit board C including the organic resin film and that the difference in the amount of released water is caused by water included in the organic resin film.

Further, when the intensity of the circuit board B including the organic resin film, which is shown in FIG. 22, is compared with that of the circuit board F not including the organic resin film, which is shown in FIG. 23, there are no significant difference in the intensities at temperatures of 100° C. or less, and the intensity of the circuit board B becomes higher when the temperature exceeds 100° C. Thus, as for the circuit boards A and E each of which was subjected to heat treatment in a reduced pressure atmosphere after formation of the alignment film, it can be considered that more water is released from the circuit board A including the organic resin film and that the difference in the amount of released water is caused by water included in the organic resin film. However, as for the circuit boards B and F each of which was subjected to heat treatment in a reduced pressure atmosphere, the difference in the amount of released water is smaller than that in the case of the circuit boards A and E and that in the case of the circuit boards C and G Accordingly, it is considered that water included in the organic resin film is effectively released by heat treatment in a reduced pressure atmosphere compared with the case where heat treatment is not performed or the case where heat treatment is performed in an air atmosphere.

The above-described results of the TDS show that the liquid crystal panel of one embodiment of the present invention, in which a liquid crystal layer is sealed between substrates without being exposed to the air (e.g., in a nitrogen atmosphere) after heat treatment at 160° C. in a reduced pressure atmosphere, contains little water in the organic resin film.

<Performance Change of Driver Circuit (Operating Margin Width)>

Next, a change in operating margin width of a scan line driver circuit included in the liquid crystal panel over time was described. Liquid crystal panels H and I, whose changes in operating margin width over time were measured, are liquid crystal panels which were totally manufactured in the same process up to and including the step of forming an alignment film in a manner similar to the circuit boards A to D which were used for the TDS. In each of the liquid crystal panels H and I, a scan line driver circuit is formed over the same substrate as a pixel, and a 3 μm-thick organic resin film containing an acrylic resin is formed over a transistor included in the scan line driver circuit.

The liquid crystal panel H was manufactured in the following manner. After formation of the alignment film, heat treatment was performed at 160° C. for one hour in a reduced pressure atmosphere of about 10⁻⁴ Pa. After that, a sealant was drawn on the counter substrate in a nitrogen atmosphere, a liquid crystal material was dropped in a region surrounded by the sealant, and the substrate and the counter substrate were bonded to each other in a reduced pressure atmosphere. Thus, the liquid crystal panel H in which a liquid crystal layer was sealed between the substrates was manufactured.

On the other hand, the liquid crystal panel I was manufactured in the following manner. After formation of the alignment film, heat treatment was performed at 150° C. for six hours in an air atmosphere. After that, a sealant was drawn on the counter substrate in an air atmosphere, a liquid crystal material was dropped in a region surrounded by the sealant, and the substrates were bonded to each other in a reduced pressure atmosphere. Thus, the liquid crystal panel I in which a liquid crystal layer was sealed between the substrates was manufactured.

An operating margin width (V) of the scan line driver circuit included in each of the liquid crystal panels H and I was examined in such a manner that a start pulse signal and a clock signal were input to sequential circuits of 959 stages included in a shift register of the scan line driver circuit, and a waveform of a signal thereby output from the sequential circuit of the last stage was observed using an oscilloscope.

As the start pulse signal, a signal having a pulse with a 68.3 μsec width which successively appears, with a frequency of 60 Hz, was used. Further, in each of the clock signal and the start pulse signal, a low voltage GVSS was −14V. The value of a high voltage GVDD where the waveform of a signal output from the sequential circuit of the last stage was disordered when the high voltage GVDD of each of the clock signal and the start pulse signal was gradually decreased from +14 V is defined as a malfunction voltage. Further, the difference between +14 V that is the highest voltage GVDD and the malfunction voltage is defined as an operating margin width.

FIG. 24 illustrates a change in an operating margin width (V) with respect to an operation time (hour) in the scan line driver circuit included in the liquid crystal panel H. Further, FIG. 25 illustrates a change in an operating margin width (V) with respect to an operation time (hour) in the scan line driver circuit included in the liquid crystal panel I.

From FIG. 24 and FIG. 25, the operating margin widths of the liquid crystal panels H and I were the same, about 22 V, at the start of the operation; however, after 220 hours, the operating margin width of the liquid crystal panel H was about 17 V, and the operating margin width of the liquid crystal panel I was about 7 V. Thus, the operating margin width of the liquid crystal panel I was decreased in a shorter time than that of the liquid crystal panel H. Therefore, it is recognized that the amount of shift in the threshold voltage of the transistor included in the scan line driver circuit of the liquid crystal panel H is smaller than that of the liquid crystal panel I.

This application is based on Japanese Patent Application serial No. 2012-227346 filed with Japan Patent Office on Oct. 12, 2012, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A method for manufacturing a liquid crystal display device comprising a first substrate including a transistor and a second substrate including a color filter, comprising the steps of: heating the first substrate under reduced pressure; heating the second substrate under reduced pressure; and dropping a liquid crystal material on the second substrate under a nitrogen atmosphere; wherein a series of the steps from heating the first substrate to dropping the liquid crystal material is performed without exposure to an air.
 2. The method for manufacturing a liquid crystal display device according to claim 1, wherein the step of heating the first substrate is performed at a temperature higher than or equal to 100° C.
 3. The method for manufacturing a liquid crystal display device according to claim 1, wherein the step of heating the second substrate is performed at a temperature higher than or equal to 100° C.
 4. The method for manufacturing a liquid crystal display device according to claim 1, further comprising the step of bonding the first substrate and the second substrate with the liquid crystal material interposed therebetween, wherein the step of bonding is performed in an atmosphere at a dew point of lower than or equal to −60° C.
 5. The method for manufacturing a liquid crystal display device according to claim 1, wherein the transistor comprises an oxide semiconductor film.
 6. The method for manufacturing a liquid crystal display device according to claim 5, wherein the oxide semiconductor film contains indium, gallium, and zinc.
 7. The method for manufacturing a liquid crystal display device according to claim 5, wherein the oxide semiconductor film comprises a crystal part.
 8. The method for manufacturing a liquid crystal display device according to claim 7, wherein a c-axis of a crystal in the crystal part is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor film.
 9. A method for manufacturing a liquid crystal display device comprising the steps of: forming a transistor over a first substrate, the transistor comprising an oxide semiconductor film which includes a channel formation region; forming an insulating film over the transistor; forming a pixel electrode over the insulating film, the pixel electrode being in electrical contact with the transistor; forming a first orientation film over the pixel electrode; heating the first substrate after forming the first orientation film under reduced pressure to perform dry treatment; forming a second orientation film over a second substrate; heating the second substrate after forming the second orientation film under reduced pressure to perform dry treatment; dropping a liquid crystal material on the second orientation film after heating the second substrate; and bonding the first substrate and the second substrate with each other with the liquid crystal material interposed therebetween.
 10. The method for manufacturing a liquid crystal display device according to claim 9, wherein the step of heating the first substrate is performed at a temperature higher than or equal to 100° C.
 11. The method for manufacturing a liquid crystal display device according to claim 9, wherein the step of heating the second substrate is performed at a temperature higher than or equal to 100° C.
 12. The method for manufacturing a liquid crystal display device according to claim 9, wherein the step of bonding is performed in an atmosphere at a dew point of lower than or equal to −60° C.
 13. The method for manufacturing a liquid crystal display device according to claim 9, wherein the oxide semiconductor film contains indium, gallium, and zinc.
 14. The method for manufacturing a liquid crystal display device according to claim 9, wherein the oxide semiconductor film comprises a crystal part.
 15. The method for manufacturing a liquid crystal display device according to claim 14, wherein a c-axis of a crystal in the crystal part is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor film.
 16. A liquid crystal display device comprising: a first substrate comprising a transistor and a plurality of first electrodes having a striped shape over the transistor; and a second substrate comprising a plurality of second electrodes having a striped shape, wherein the first substrate and the second substrate are bonded with each other so that the plurality of first electrodes intersect with the plurality of second electrodes, and wherein capacitances between the plurality of first electrodes and the plurality of second electrodes serve as a touch sensor.
 17. The liquid crystal display device according to claim 16, wherein the transistor comprises an oxide semiconductor film.
 18. The liquid crystal display device according to claim 17, wherein the oxide semiconductor film contains indium, gallium, and zinc.
 19. The liquid crystal display device according to claim 17, wherein the oxide semiconductor film comprises a crystal part.
 20. The liquid crystal display device according to claim 19, wherein a c-axis of a crystal in the crystal part is aligned in a direction substantially perpendicular to a top surface of the oxide semiconductor film. 